Microchip Technology dsPIC33F Family Instrukcja Użytkownika Pobierz pdf (Strona 15)

Section 11. Timers

Timers

11.5 TIMER INTERRUPTS

A timer interrupt is generated:

• On a period match for Timer mode or Synchronous/Asynchronous Counter mode (refer to

Figure 11-4)

• On falling edge of the “gate” signal at the TxCK pin for Gated Timer mode (refer to

Figure 11-5)

The Timer Interrupt Flag bit (TxIF) must be cleared in software.

A timer is enabled as a source of interrupt via the respective Timer Interrupt Enable bit (TxIE).

The Interrupt Priority Level bits (TxIP<2:0>) must be written with a non-zero value for the timer

to be a source of interrupt. For further details, refer to Section 6. “Interrupts” (DS70184).

Note: A special case occurs when the period register, PRx, is loaded with 0x0000 and the

timer is enabled. No timer interrupts are generated for this configuration.

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