Microchip Technology Audio Digital-to-Analog Converter Instrukcja Użytkownika Pobierz pdf (Strona 23)

DAC Clock

z Clock Reference

− Auxiliary Oscillator (Separate from System Clock)

− Primary Oscillator

− FRC w/ PLL

z DAC Clock (DACCLK) = Sampling Rate Frequency x 256

Example:

Sample Rate = 100 ksps To achieve DACCLK:

DACCLK = 256 x 100,000 25.6 MHz – Auxiliary Oscillator

DACCLK = 25.6 Msps DACFDIV = 0b0000000

Now lets take a look at how to select and configure the DAC reference clock. The

DAC clock can be generated from either the Primary Oscillator, the Auxiliary

Oscillator or can even be generated from the internal FRC with PLL. The Auxiliary

Oscillator is tied to the Secondary Oscillator pins on the device (SOSCO and

SOSCI) and allows the DAC clock to operate separately from the system clock. The

Auxiliary Oscillator mode bits (AOSCMD<1:0>) in the Auxiliary Clock Control

divider bits (APSTSCLR <2:0>) in the Auxiliary Clock Control Register allow any

of the DAC reference clocks to be divided by any one of the predetermined

postscalar settings. The DAC module itself also has a clock divider that can be used

to scale the input clock to an exact input frequency. When all is said and done the

DAC clock (DACCLK) must be equal to Sampling Rate Frequency x 256.

Now lets take a quick look at an example. Suppose the sample rate we want to

achieve is 100ksps. This would mean that the required DACCLK must be equal to

100ksps times 256. To obtain the 25.6MHz clock we will select an external crystal

for the Auxiliary Oscillator of the same frequency. Since we have the exact

oscillator frequency all postscalars will be set to divide by 1. So DACFDIV = 0x0

and APSTSCLR = 0x0.

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Microchip Technology Audio Digital-to-Analog Converter Instrukcja Użytkownika Strona 23